The present invention relates to an improved circuit structure for reducing leakage current due to the subthreshold characteristic of a MOS transistor, a semiconductor integrated circuit in which the operating voltage is kept constant, and a technique effectively applied to a large-capacity DRAM (Dynamic Random Access Memory) having a storage capacity of, for example, 256 Mbit to 1 Gbit or more.
In the case of an extremely-integrated semiconductor integrated circuit such as a DRAM, the operating voltage is lowered to 2 to 2.5 V because elements are microminiaturized and the threshold voltage of a MOS transistor is lowered to 0.15 to 0.2 V (conventionally, approx. 0.4 V) for speed-up. However, the leakage current (subthreshold current) due to the subthreshold characteristic of a MOS transistor is a problem. The subthreshold current is a leakage current which flows when the gate voltage is equal to or lower than a threshold voltage and the surface is weakly inverted.
Reducing the threshold voltage is disclosed in Japanese Patent Laid-Open Nos. 8-138381/1996, 6-232348/1994, 6-203558/1994, 5-210976/1993, and 5-347550/1993.